1. Field of the Invention
The present invention is directed to digital data transmission employing a data bus and data storage in a solid state memory which is accessed by the bus. More particularly, the present invention is directed to a bus system in which a variable number of bus lines are employed to transmit data and a variable number of storage locations corresponding to different data word locations in a memory are employed. The invention has a particular application with respect to solid state data recorders such as those employed in space missions in satellites or manned spacecraft. Solid state data recorders employ solid state memory devices to store data, in contrast to the typical storage medium of magnetic tape. Such recorders can provide improved reliability in that they do not require complicated tape handling mechanisms. In solid state recorders, data is stored by appropriately addressing a random access memory (RAM) and recording a series of data words of a predetermined number of bits each.
Since there are no moving mechanisms for tape handling or the like, solid state recorders can provide a high degree of reliability. However, such recorders are typically very expensive due to the high cost of memory. Moreover, in the space environment where repair generally is not possible during the course of a mission, provision must be made to ensure a certain recording capacity throughout the life of the mission. Thus, sufficient overall memory capacity must be provided such that even after failure of a number of memory devices during a mission sufficient overall capacity will be retained. In effect, "spare" memory devices must be provided to replace failed devices in order to maintain a nominal recording capacity. The necessity to provide spare devices further increases the overall cost of the system.
2. Description of the Prior Art
Various solid state recorders have been proposed in the past, such as that shown in U.S. Pat. No. 4,970,648 to Capots. The recorder disclosed in this patent has the capability of detecting errors in its memory and avoiding use of portions of the memory that have errors. The memory is controlled by a control CPU on the basis of "pages", which are the smallest portion of the memory array which has meaning to the CPU. The system evaluates the memory to detect pages which have non-correctable errors. Such pages are then removed from use. In this fashion, failed memory locations are avoided and reliability is maintained.
Although a system in which memory pages are removed provides the necessary reliability, the cost can be extremely high in terms of memory requirements. This is especially so since failures are very often isolated in a relatively small memory area (even an individual storage location), and the removal of an entire page of memory often results in the removal of a significant amount of usable memory along with failed memory. The result is that greater memory overhead is required to maintain the specified data capacity, and cost is significantly increased.